(1) Field of the Invention
The present invention generally relates to sequential logic circuits, and more particularly to a sequential logic circuit which includes state holding circuits.
(2) Description of the Prior Art
Digital logic circuits are categorized as being either a combination logic circuit or a sequential logic circuit. The combination logic circuit has an output signal which is defined by only the current state of a current input signal. The sequential logic circuit has an output signal which is defined by not only the current state of the input signal but also the previous state thereof. A basic circuit necessary to configure the sequential logic circuit is composed of a latch circuit and a flip-flop. A flip-flop can be formed by two latch circuits.
Normally, a D-type flip-flop is user to form a sequential logic circuit. Data is latched in the flip-flop via its data terminal D in synchronism with a clock signal applied to a clock terminal D thereof. As is well known, it is necessary to use a large number of normal bipolar transistors in order to hold the state of a signal. Use of a large number of bipolar transistors is disadvantageous in terms of integration density and operating speed.
It is possible to use an element having a hysteresis characteristic in order to hold the state of a signal. In principle, a single transistor having a hysteresis characteristic has the function of holding the state of a signal. However, it is impossible to form the sequential logic circuit by simply connecting transistors having hysteresis characteristics without taking into account a clock signal control procedure and an arrangement for outputting an output signal.